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Using %d RX descriptors instead of %d! Can not allocate stats memory Can not allocate multicast setup array dmacDMA Coalesceeee_disabledDisable Energy Efficient EthernetThe EEPROM Checksum Is Not Valid EEPROM read error while reading MAC address Invalid MAC address PHY reset is blocked due to SOL/IDER session. vlan_configvlan_unconfig Interface EEPROM Dump: Offset 0x0000 0x00%x0 %04x Unable to allocate bus resource: memory Unable to map MSIX table MSIX Configuration Problem, %d vectors configured, but %d queues wanted! Using MSIX interrupts with %d vectors Using an MSI interrupt Using a Legacy interrupt Unable to allocate queue memory Unable to allocate TX ring memory Unable to allocate RX ring memory %s:tx(%d)Unable to allocate TX Descriptor memory Critical Failure setting up transmit buffers %s:rx(%d)Unable to allocate RxDescriptor memory Critical Failure setting up receive buffers %s: bus_dma_tag_create failed: %d igb_dma_malloc%s: bus_dmamem_alloc(%ju) failed: %d %s: bus_dmamap_load failed: %d Unable to allocate TX DMA tag Unable to allocate tx_buffer memory Unable to create TX DMA map Unable to allocate rx_buffer memory Unable to create RX DMA tag Unable to create RX payload DMA tag Unable to create RX head DMA maps Unable to create RX packet DMA maps /usr/src/sys/modules/igb/../../dev/e1000/if_igb.cCould not setup receive structures LRO Initialization failed! Watchdog timeout -- resetting Queue(%d) tdh = %d, hw tdt = %d TX(%d) desc avail = %d,Next TX to Clean = %d can not allocate ifnet structure Media change is blocked due to SOL/IDER session. CSUM_TSO but no supported IP version (0x%04x)Unsupported media type Hardware Initialization Failed DMA Coalescing enabled RXTXFullNoneLink is up %d Mbps %s, Flow Control: %s Full DuplexHalf DuplexLink is Down droppedLUDriver dropped packetslink_irqLink MSIX IRQ Handledmbuf_defrag_failDefragmenting mbuf chain failedtx_dma_failDriver tx dma failure in xmitrx_overrunsRX overrunswatchdog_timeoutsWatchdog timeoutsdevice_controlDevice Control Registerrx_controlReceiver Control Registerinterrupt_maskInterrupt Maskextended_int_maskExtended Interrupt Masktx_buf_allocTransmit Buffer Packet Allocationrx_buf_allocReceive Buffer Packet Allocationfc_high_waterIUFlow Control High Watermarkfc_low_waterFlow Control Low Watermarkqueue%dNQueue Nameinterrupt_rateInterrupt Ratetxd_headTransmit Descriptor Headtxd_tailTransmit Descriptor Tailno_desc_availQQueue Descriptors Unavailabletx_packetsQUQueue Packets Transmittedrxd_headReceive Descriptor Headrxd_tailReceive Descriptor Tailrx_packetsQueue Packets Receivedrx_bytesQueue Bytes Receivedlro_queuedLRO Queuedlro_flushedLRO Flushedmac_statsMAC Statisticsgood_pkts_recvdGood Packets Receivedgood_pkts_txdGood Packets Transmittedgood_octets_recvdGood Octets Receivedgood_octets_txdGood Octets Transmittedmcast_pkts_recvdMulticast Packets Receivedexcess_collExcessive collisionssingle_collSingle collisionsmultiple_collMultiple collisionslate_collLate collisionscollision_countCollision Countsymbol_errorsSymbol Errorssequence_errorsSequence Errorsdefer_countDefer Countmissed_packetsMissed Packetsrecv_length_errorsReceive Length Errorsrecv_no_buffReceive No Buffersrecv_undersizeReceive Undersizerecv_fragmentedFragmented Packets Receivedrecv_oversizeOversized Packets Receivedrecv_jabberRecevied Jabberrecv_errsReceive Errorscrc_errsCRC errorsalignment_errsAlignment Errorstx_no_crsTransmit with No CRScoll_ext_errsCollision/Carrier extension errorsxon_recvdXON Receivedxon_txdXON Transmittedxoff_recvdXOFF Receivedxoff_txdXOFF Transmittedunsupported_fc_recvdUnsupported Flow Control Receivedmgmt_pkts_recvdManagement Packets Receivedmgmt_pkts_dropManagement Packets Droppedmgmt_pkts_txdManagement Packets Transmittedtotal_pkts_recvdTotal Packets Receivedbcast_pkts_recvdBroadcast Packets Receivedrx_frames_6464 byte frames receivedrx_frames_65_12765-127 byte frames receivedrx_frames_128_255128-255 byte frames receivedrx_frames_256_511256-511 byte frames receivedrx_frames_512_1023512-1023 byte frames receivedrx_frames_1024_15221023-1522 byte frames receivedtotal_octets_recvdTotal Octets Receivedtotal_octets_txdTotal Octets Transmittedtotal_pkts_txdTotal Packets Transmittedbcast_pkts_txdBroadcast Packets Transmittedmcast_pkts_txdMulticast Packets Transmittedtx_frames_6464 byte frames transmittedtx_frames_65_12765-127 byte frames transmittedtx_frames_128_255128-255 byte frames transmittedtx_frames_256_511256-511 byte frames transmittedtx_frames_512_1023512-1023 byte frames transmittedtx_frames_1024_15221024-1522 byte frames transmittedtso_txdTSO Contexts Transmittedtso_ctx_failTSO Contexts FailedinterruptsInterrupt StatisticsassertsInterrupt Assertion Countrx_pkt_timerInterrupt Cause Rx Pkt Timer Expire Countrx_abs_timerInterrupt Cause Rx Abs Timer Expire Counttx_pkt_timerInterrupt Cause Tx Pkt Timer Expire Counttx_abs_timerInterrupt Cause Tx Abs Timer Expire Counttx_queue_emptyInterrupt Cause Tx Queue Empty Counttx_queue_min_threshInterrupt Cause Tx Queue Min Thresh Countrx_desc_min_threshInterrupt Cause Rx Desc Min Thresh Countrx_overrunInterrupt Cause Receiver Overrun CounthostHost to Card Statisticsbreaker_tx_pktCircuit Breaker Tx Packet Counthost_tx_pkt_discardHost Transmit Discarded Packetsrx_pktRx Packets To Hostbreaker_rx_pktsCircuit Breaker Rx Packet Countbreaker_rx_pkt_dropCircuit Breaker Rx Dropped Counttx_good_pktHost Good Packets Tx Countbreaker_tx_pkt_dropHost Tx Circuit Breaker Dropped Countrx_good_bytesHost Good Octets Received Counttx_good_bytesHost Good Octets Transmit Countlength_errorsLength Errorsserdes_violation_pktSerDes/SGMII Code Violation Pkt Countheader_redir_missedHeader Redirection Missed Packet CountUnable to allocate bus resource: MSIX Queue Interrupt Failed to register Queue handlerque %dBound queue %d to cpu %d igb_que%s que (qid %d)%s queUnable to allocate bus resource: MSIX Link Interrupt Failed to register Link handlerlinkRefresh mbufs: hdr dmamap load failure - %d Refresh mbufs: payload dmamap load failure - %d Unable to allocate bus resource: interrupt igb_taskq%s taskqFailed to register fast interrupt handler: %d Vlan in use, detach first etherIGB driver parametersrxdNumber of receive descriptors per queuetxdNumber of transmit descriptors per queueEnable adaptive interrupt moderationenable_msixEnable MSI-X interruptsmax_interrupt_rateMaximum interrupts per secondbuf_ring_sizeSize of the bufringheader_splitEnable receive mbuf header splitnum_queuesNumber of queues to configure, 0 indicates autoconfigurerx_process_limitMaximum number of received packets to process at a time, -1 means unlimitedtx_process_limitMaximum number of sent packets to process at a time, -1 means unlimitedMAC Initialization Error mac.init_mac_params was NULL NVM Initialization Error nvm.init_nvm_params was NULL PHY Initialization Error phy.init_phy_params was NULL Mailbox Initialization Error mbx.init_mbx_params was NULL e1000_set_mac_type ERROR: MAC type could not be set properly. ERROR: Registers not mapped Hardware not supported e1000_init_phy_ops_generic e1000_null_set_page e1000_null_read_reg e1000_null_phy_generic e1000_null_lplu_state e1000_null_write_reg e1000_read_i2c_byte_null e1000_write_i2c_byte_null e1000_check_reset_block e1000_get_phy_id e1000_phy_reset_dsp_generic e1000_read_phy_reg_mdic PHY Address %d is out of range MDI Read did not complete MDI Error MDI Read offset error - requested %d, returned %d e1000_write_phy_reg_mdic MDI Write did not complete MDI Write offset error - requested %d, returned %d e1000_read_phy_reg_i2c I2CCMD Read did not complete I2CCMD Error bit set e1000_write_phy_reg_i2c PHY I2C Address %d is out of range. I2CCMD Write did not complete e1000_read_sfp_data_byte I2CCMD command address exceeds upper limit e1000_write_sfp_data_byte e1000_read_phy_reg_m88 e1000_write_phy_reg_m88 e1000_set_page_igp Setting page 0x%x e1000_copper_link_setup_82577 Error resetting the PHY. e1000_copper_link_setup_m88 Error committing the PHY changes e1000_copper_link_setup_m88_gen2 e1000_copper_link_setup_igp Error Disabling LPLU D3 Error Disabling LPLU D0 e1000_phy_setup_autoneg autoneg_advertised %x Advertise 10mb Half duplex Advertise 10mb Full duplex Advertise 100mb Half duplex Advertise 100mb Full duplex Advertise 1000mb Half duplex request denied! Advertise 1000mb Full duplex Flow control param set incorrectly Auto-Neg Advertising %x e1000_copper_link_autoneg Reconfiguring auto-neg advertisement params Error Setting up Auto-Negotiation Restarting Auto-Neg Error while waiting for autoneg to complete e1000_setup_copper_link_generic Forcing Speed and Duplex Error Forcing Speed and Duplex Valid link established!!! Unable to establish link!!! e1000_phy_force_speed_duplex_igp IGP PSCR: %X Waiting for forced speed/duplex link on IGP phy. Link taking longer than expected. e1000_phy_force_speed_duplex_m88 M88E1000 PSCR: %X Waiting for forced speed/duplex link on M88 phy. e1000_phy_force_speed_duplex_ife IFE PMC: %X Waiting for forced speed/duplex link on IFE phy. e1000_phy_force_speed_duplex_setup Half Duplex Full Duplex Forcing 100mb Forcing 10mb e1000_set_d3_lplu_state_generic e1000_check_downshift_generic e1000_check_polarity_m88 e1000_check_polarity_igp e1000_check_polarity_ife e1000_phy_has_link_generic e1000_get_cable_length_m88 e1000_get_cable_length_m88_gen2 e1000_get_cable_length_igp_2 e1000_get_phy_info_m88 Phy info is only valid for copper media Phy info is only valid if link is up e1000_get_phy_info_igp e1000_get_phy_info_ife e1000_phy_sw_reset_generic e1000_phy_hw_reset_generic e1000_get_cfg_done_generic Running IGP 3 PHY init script e1000_write_phy_reg_bm e1000_read_phy_reg_bm e1000_read_phy_reg_bm2 e1000_write_phy_reg_bm2 e1000_enable_phy_wakeup_reg_access_bm Could not set Port Control page Could not read PHY register %d.%d Could not write PHY register %d.%d e1000_disable_phy_wakeup_reg_access_bm Could not restore PHY register %d.%d e1000_link_stall_workaround_hv e1000_check_polarity_82577 e1000_phy_force_speed_duplex_82577 Waiting for forced speed/duplex link on 82577 phy e1000_get_phy_info_82577 e1000_get_cable_length_82577 e1000_write_phy_reg_gs40g e1000_read_phy_reg_gs40g e1000_read_phy_reg_mphy e1000_write_phy_reg_mphy ERROR READING mPHY control register, phy is busy. __e1000_read_phy_reg_igp e1000_write_phy_reg_igp __e1000_read_kmrn_reg e1000_write_kmrn_reg_generic e1000_wait_autoneg e1000_access_phy_wakeup_reg_bm Attempting to access page %d while gig enabled. Could not enable PHY wakeup reg access Accessing PHY page %d reg 0x%x Could not write address opcode to page %d Could not access PHY reg %d.%d __e1000_read_phy_reg_hv reading PHY page %d (or 0x%x shifted) reg 0x%x e1000_access_phy_debug_regs_hv Could not write the Address Offset port register Could not access the Data port register __e1000_write_phy_reg_hv writing PHY page %d (or 0x%x shifted) reg 0x%x e1000_init_nvm_ops_generic e1000_null_read_nvm e1000_null_nvm_generic e1000_null_led_default e1000_null_write_nvm e1000_poll_eerd_eewr_done e1000_acquire_nvm_generic Could not acquire NVM grant e1000_stop_nvm e1000_release_nvm_generic e1000_read_nvm_spi nvm parameter(s) out of bounds e1000_read_nvm_microwire e1000_read_nvm_eerd NVM read error: %d e1000_write_nvm_spi e1000_write_nvm_microwire NVM Write did not complete e1000_read_pba_string_generic Flashless no PBA string PBA string buffer was null NVM Read Error NVM PBA number is not stored as string PBA string buffer too small NVM PBA number section invalid length e1000_read_pba_length_generic PBA buffer size was null e1000_get_pba_block_size e1000_validate_nvm_checksum_generic NVM Checksum Invalid e1000_update_nvm_checksum NVM Read Error while updating checksum. NVM Write Error while updating checksum. e1000_ready_nvm_eeprom SPI NVM Status error e1000_standby_nvm e1000_shift_out_eec_bits e1000_shift_in_eec_bits e1000_reload_nvm_generic e1000_init_mac_ops_generic e1000_null_ops_generic e1000_null_mac_generic e1000_null_link_info e1000_null_mng_mode e1000_null_update_mc e1000_null_write_vfta e1000_null_rar_set e1000_null_set_obff_timer e1000_get_bus_info_pci_generic e1000_get_bus_info_pcie_generic e1000_clear_vfta_generic e1000_write_vfta_generic e1000_init_rx_addrs_generic Programming MAC Address into RAR[0] Clearing RAR[1-%u] e1000_check_alt_mac_addr_generic NVM Read Error Ignoring Alternate Mac Address with MC bit set e1000_hash_mc_addr_generic e1000_update_mc_addr_list_generic e1000_pcix_mmrbc_workaround_generic e1000_clear_hw_cntrs_base_generic e1000_check_for_copper_link Error configuring flow control e1000_check_for_fiber_link_generic NOT Rx'ing /C/, disable AutoNeg and force link. Rx'ing /C/, enable AutoNeg and stop forcing link. e1000_check_for_serdes_link_generic SERDES: Link up - forced. SERDES: Link down - force failed. SERDES: Link up - autoneg completed successfully. SERDES: Link down - invalid codewords detected in autoneg. SERDES: Link down - no sync. SERDES: Link down - autoneg failed e1000_set_default_fc_generic e1000_setup_link_generic After fix-ups FlowControl is now = %x Initializing the Flow Control address, type and timer regs e1000_commit_fc_settings_generic Flow control param set incorrectly e1000_poll_fiber_serdes_link_generic Never got a valid link from auto-neg!!! Error while checking for link Valid Link Found e1000_setup_fiber_serdes_link_generic Auto-negotiation enabled No signal detected e1000_set_fc_watermarks_generic e1000_force_mac_fc_generic hw->fc.current_mode = %u e1000_config_fc_after_link_up_generic Error forcing flow control settings Copper PHY and Auto Neg has not completed. Flow Control = FULL. Flow Control = Rx PAUSE frames only. Flow Control = Tx PAUSE frames only. Flow Control = NONE. Error getting link speed and duplex PCS Auto Neg has not completed. e1000_get_speed_and_duplex_copper_generic 1000 Mbs, 100 Mbs, 10 Mbs, Full Duplex Half Duplex e1000_get_speed_and_duplex_fiber_serdes_generic e1000_get_hw_semaphore_generic Driver can't access device - SMBI bit is set. Driver can't access the NVM e1000_put_hw_semaphore_generic e1000_get_auto_rd_done_generic Auto read by HW from NVM has not completed. e1000_valid_led_default_generic e1000_id_led_init_generic e1000_setup_led_generic e1000_cleanup_led_generic e1000_blink_led_generic e1000_led_on_generic e1000_led_off_generic e1000_set_pcie_no_snoop_generic e1000_disable_pcie_master_generic Master requests are pending. e1000_reset_adaptive_generic Not in Adaptive IFS mode! e1000_update_adaptive_generic e1000_validate_mdi_setting_crossover_generic e1000_write_8bit_ctrl_reg_generic Reg %08x did not indicate ready e1000_rar_set_generic e1000_config_collision_dist_generic e1000_validate_mdi_setting_generic Invalid MDI setting detected e1000_calculate_checksum e1000_mng_enable_host_if_generic ARC subsystem not valid. E1000_HOST_EN bit disabled. Previous command timeout failed . e1000_check_mng_mode_generic e1000_enable_tx_pkt_filtering_generic e1000_mng_write_cmd_header_generic e1000_mng_host_if_write_generic e1000_mng_write_dhcp_info_generic e1000_enable_mng_pass_thru e1000_host_interface_command Hardware doesn't support host interface command. Firmware is not present. Buffer length failure. Command has failed with no status valid. e1000_load_firmware Hardware doesn't support loading FW by the driver E1000_HICR_MEMORY_BASE_EN bit disabled. FW reset failed. New FW did not start within timeout period. e1000_init_function_pointers_80003es2lan e1000_init_mac_params_80003es2lan e1000_setup_copper_link_80003es2lan e1000_write_kmrn_reg_80003es2lan e1000_acquire_mac_csr_80003es2lan e1000_acquire_swfw_sync_80003es2lan Driver can't access resource, SW_FW_SYNC timeout. e1000_release_mac_csr_80003es2lan e1000_release_swfw_sync_80003es2lan e1000_read_kmrn_reg_80003es2lan e1000_copper_link_setup_gg82563_80003es2lan Error Resetting the PHY e1000_reset_hw_80003es2lan PCI-E Master disable polling has failed. Masking off all interrupts Issuing a global reset to MAC Error disabling far-end loopback e1000_acquire_phy_80003es2lan e1000_release_phy_80003es2lan e1000_init_hw_80003es2lan Error initializing identification LED Initializing the IEEE VLAN Zeroing the MTA e1000_initialize_hw_bits_80003es2lan e1000_read_mac_addr_80003es2lan e1000_clear_hw_cntrs_80003es2lan e1000_get_link_up_info_80003es2lan e1000_init_nvm_params_80003es2lan e1000_acquire_nvm_80003es2lan e1000_release_nvm_80003es2lan e1000_write_nvm_80003es2lan e1000_init_phy_params_80003es2lan e1000_get_cfg_done_80003es2lan MNG configuration cycle has not completed. e1000_phy_force_speed_duplex_80003es2lan GG82563 PSCR: %X Waiting for forced speed/duplex link on GG82563 phy. e1000_get_cable_length_80003es2lan e1000_read_phy_reg_gg82563_80003es2lan e1000_write_phy_reg_gg82563_80003es2lan e1000_configure_on_link_up e1000_configure_kmrn_for_1000 e1000_configure_kmrn_for_10_100 e1000_init_function_pointers_82542 e1000_init_mac_params_82542 e1000_get_bus_info_82542 e1000_reset_hw_82542 Disabling MWI on 82542 rev 2 Masking off all interrupts Issuing a global reset to 82542/82543 MAC e1000_init_hw_82542 Disabling MWI on 82542 rev 2.0 Zeroing the MTA e1000_setup_link_82542 After fix-ups FlowControl is now = %x Initializing Flow Control address, type and timer regs e1000_read_mac_addr NVM Read Error e1000_rar_set_82542 e1000_led_on_82542 e1000_led_off_82542 e1000_clear_hw_cntrs_82542 e1000_init_nvm_params_82542 e1000_init_phy_params_82542 e1000_init_function_pointers_82541 e1000_init_script_state_82541 Initialization script not necessary. e1000_init_mac_params_82541 e1000_reset_hw_82541 Masking off all interrupts Issuing a global reset to 82541/82547 MAC e1000_phy_init_script_82541 e1000_init_hw_82541 Error initializing identification LED Initializing the IEEE VLAN Zeroing the MTA e1000_setup_copper_link_82541 e1000_check_for_link_82541 Error configuring flow control e1000_config_dsp_after_link_change_82541 Error getting link speed and duplex e1000_get_link_up_info_82541 e1000_read_mac_addr NVM Read Error e1000_setup_led_82541 e1000_cleanup_led_82541 e1000_clear_hw_cntrs_82541 e1000_init_nvm_params_82541 e1000_init_phy_params_82541 e1000_get_cable_length_igp_82541 e1000_phy_hw_reset_82541 e1000_set_d3_lplu_state_82541 e1000_init_function_pointers_82543 e1000_set_tbi_compatibility_82543 TBI compatibility workaround for 82543 only. e1000_tbi_sbp_enabled_82543 e1000_init_mac_params_82543 e1000_reset_hw_82543 Masking off all interrupts Issuing a global reset to 82543/82544 MAC e1000_set_tbi_sbp_82543 e1000_tbi_compatibility_enabled_82543 e1000_init_hw_82543 Zeroing the MTA e1000_setup_link_82543 NVM Read Error e1000_setup_copper_link_82543 Forcing Speed and Duplex Error Forcing Speed and Duplex Valid link established!!! Unable to establish link!!! e1000_phy_force_speed_duplex_82543 e1000_config_mac_to_phy_82543 e1000_setup_fiber_link_82543 Auto-negotiation enabled No signal detected e1000_check_for_copper_link_82543 Error configuring MAC to PHY settings Error configuring flow control Error getting link speed and duplex e1000_check_for_fiber_link_82543 NOT RXing /C/, disable AutoNeg and force link. RXing /C/, enable AutoNeg and stop forcing link. e1000_write_vfta_82543 e1000_read_mac_addr e1000_led_on_82543 e1000_led_off_82543 e1000_clear_hw_cntrs_82543 e1000_init_nvm_params_82543 e1000_init_phy_params_82543 Resetting PHY during init failed. e1000_read_phy_reg_82543 PHY Address %d is out of range e1000_phy_hw_reset_82543 e1000_write_phy_reg_82543 e1000_init_phy_disabled_82543 e1000_init_function_pointers_82540 e1000_init_mac_params_82540 e1000_reset_hw_82540 Masking off all interrupts Issuing a global reset to 82540/82545/82546 MAC e1000_init_hw_82540 Error initializing identification LED Initializing the IEEE VLAN Zeroing the MTA e1000_setup_copper_link_82540 e1000_set_phy_mode_82540 e1000_setup_fiber_serdes_link_82540 e1000_adjust_serdes_amplitude_82540 e1000_set_vco_speed_82540 e1000_read_mac_addr NVM Read Error e1000_clear_hw_cntrs_82540 e1000_init_nvm_params_82540 e1000_read_emi_reg_locked e1000_set_eee_pchlan CABLE_DISCONNECTED %s set after %dmsec notError in ULP enable flow: %d ULP_CONFIG_DONE cleared after %dmsec Error in ULP disable flow: %d e1000_init_function_pointers_ich8lan e1000_configure_k1_ich8lan e1000_copy_rx_addrs_to_phy_ich8lan e1000_lv_jumbo_workaround_ich8lan e1000_set_kmrn_lock_loss_workaround_ich8lan Workaround applies to ICH8 only. e1000_igp3_phy_powerdown_workaround_ich8lan e1000_gig_downshift_workaround_ich8lan e1000_suspend_workarounds_ich8lan e1000_resume_workarounds_pchlan Failed to init PHY flow ret_val=%d Failed to setup iRST Error %d in resume workarounds __e1000_access_emi_reg_locked e1000_toggle_lanphypc_pch_lpt e1000_init_mac_params_ich8lan e1000_get_bus_info_ich8lan e1000_reset_hw_ich8lan PCI-E Master disable polling has failed. Masking off all interrupts Issuing a global reset to ich8lan /usr/src/sys/modules/igb/../../dev/e1000/e1000_ich8lan.ce1000_gate_hw_phy_config_ich8lan e1000_acquire_swflag_ich8lan SW has already locked the resource. Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x) e1000_post_phy_reset_ich8lan e1000_hv_phy_workarounds_ich8lan e1000_set_mdio_slow_mode_hv e1000_k1_gig_workaround_hv e1000_lv_phy_workarounds_ich8lan e1000_sw_lcd_config_ich8lan e1000_init_hw_ich8lan Error initializing identification LED Zeroing the MTA e1000_initialize_hw_bits_ich8lan e1000_phy_hw_reset_ich8lan e1000_setup_link_ich8lan After fix-ups FlowControl is now = %x e1000_setup_copper_link_ich8lan e1000_check_for_copper_link_ich8lan Error configuring flow control e1000_platform_pm_pch_lpt max_frame_size not set. Speed not set. Invalid LTR latency scale %d Invalid high water mark %d e1000_k1_workaround_lv e1000_get_link_up_info_ich8lan e1000_kmrn_lock_loss_workaround_ich8lan e1000_clear_hw_cntrs_ich8lan e1000_check_mng_mode_ich8lan e1000_cleanup_led_ich8lan e1000_led_on_ich8lan e1000_led_off_ich8lan e1000_rar_set_pch2lan SHRA[%d] might be locked by ME - FWSM=0x%8.8x Failed to write receive address at index %d e1000_release_swflag_ich8lan Semaphore unexpectedly released by sw/fw/hw e1000_update_mc_addr_list_pch2lan e1000_check_mng_mode_pchlan e1000_id_led_init_pchlan e1000_setup_led_pchlan e1000_cleanup_led_pchlan e1000_led_on_pchlan e1000_led_off_pchlan e1000_rar_set_pch_lpt e1000_setup_copper_link_pch_lpt e1000_set_obff_timer_pch_lpt e1000_init_nvm_params_ich8lan ERROR: Flash registers not mapped &dev_spec->nvm_mutexnetwork driver&dev_spec->swflag_mutexe1000_acquire_nvm_ich8lan e1000_release_nvm_ich8lan e1000_read_nvm_spt nvm parameter(s) out of bounds Could not detect valid bank, assuming bank 0 NVM read error: %d e1000_valid_nvm_bank_detect_ich8lan ERROR: No valid NVM bank present Unable to determine valid NVM bank via EEC - reading flash signature e1000_read_flash_data_ich8lan Timeout error - flash cycle did not complete. e1000_flash_cycle_init_ich8lan Flash descriptor invalid. SW Sequencing must be used. Flash controller busy, cannot get access e1000_flash_cycle_ich8lan e1000_read_flash_dword_ich8lan e1000_update_nvm_checksum_spt Flash commit failed. NVM update error: %d e1000_erase_flash_bank_ich8lan e1000_retry_write_flash_dword_ich8lan Retrying Byte %8.8X at offset %u e1000_write_flash_data32_ich8lan e1000_read_nvm_ich8lan e1000_read_flash_word_ich8lan e1000_update_nvm_checksum_ich8lan e1000_retry_write_flash_byte_ich8lan Retrying Byte %2.2X at offset %u e1000_write_flash_byte_ich8lan e1000_write_ich8_data e1000_valid_led_default_ich8lan NVM Read Error e1000_validate_nvm_checksum_ich8lan e1000_write_nvm_ich8lan e1000_init_phy_params_ich8lan Cannot determine PHY addr. Erroring out e1000_check_reset_block_ich8lan e1000_get_cfg_done_ich8lan Auto Read Done did not complete PHY Reset Asserted not set - needs delay EEPROM not present e1000_lan_init_done_ich8lan LAN_INIT_DONE not set, increase timeout e1000_set_d0_lplu_state_ich8lan e1000_set_d3_lplu_state_ich8lan e1000_init_phy_params_pchlan e1000_set_lplu_state_pchlan e1000_calc_rx_da_crc e1000_oem_bits_config_ich8lan Unsupported SMB frequency in PHY e1000_init_phy_workarounds_pchlan Failed to initialize PHY flow Required LANPHYPC toggle blocked by ME e1000_init_function_pointers_82571 e1000_check_phy_82574 e1000_get_laa_state_82571 e1000_set_laa_state_82571 e1000_init_mac_params_82571 Please update your 82571 Bootagent e1000_setup_fiber_serdes_link_82571 e1000_check_for_serdes_link_82571 AN_UP -> AN_PROG FORCED_UP -> AN_PROG AN_PROG -> AN_UP AN_PROG -> DOWN Error config flow control AN_PROG -> FORCED_UP DOWN -> AN_PROG ANYSTATE -> DOWN ANYSTATE -> AN_PROG e1000_setup_copper_link_82571 e1000_reset_hw_82571 PCI-E Master disable polling has failed. Masking off all interrupts Issuing a global reset to MAC e1000_get_hw_semaphore_82573 Driver can't access the PHY e1000_get_hw_semaphore_82574 /usr/src/sys/modules/igb/../../dev/e1000/e1000_82571.ce1000_put_hw_semaphore_82573 e1000_put_hw_semaphore_82574 e1000_init_hw_82571 Error initializing identification LED Initializing the IEEE VLAN Zeroing the MTA e1000_initialize_hw_bits_82571 e1000_setup_link_82571 e1000_clear_vfta_82571 e1000_read_mac_addr_82571 e1000_clear_hw_cntrs_82571 e1000_check_mng_mode_82574 e1000_led_on_82574 e1000_init_nvm_params_82571 e1000_acquire_nvm_82571 e1000_get_hw_semaphore_82571 Driver can't access device - SMBI bit is set. Driver can't access the NVM e1000_put_hw_semaphore_generic e1000_release_nvm_82571 e1000_update_nvm_checksum_82571 e1000_validate_nvm_checksum_82571 e1000_fix_nvm_checksum_82571 e1000_valid_led_default_82571 NVM Read Error e1000_write_nvm_82571 e1000_write_nvm_eewr_82571 nvm parameter(s) out of bounds e1000_init_phy_params_82571 &hw->dev_spec._82571.swflag_mutexnetwork driverError getting PHY ID PHY ID unknown: type = 0x%08x e1000_set_d0_lplu_state_82571 e1000_get_cfg_done_82571 MNG configuration cycle has not completed. e1000_set_d0_lplu_state_82574 e1000_set_d3_lplu_state_82574 e1000_get_phy_id_82571 e1000_init_nvm_params_82575 e1000_init_function_pointers_82575 e1000_init_hw_82575 Error initializing identification LED Initializing the IEEE VLAN Zeroing the MTA Zeroing the UTA e1000_rx_fifo_flush_82575 Queue disable timed out after 10ms e1000_read_emi_reg e1000_initialize_M88E1512_phy Error committing the PHY changes e1000_initialize_M88E1543_phy e1000_set_eee_i350 LPI Clock Stop Bit should not be set! e1000_set_eee_i354 e1000_get_eee_status_i354 e1000_write_vfta_350 e1000_set_i2c_bb e1000_read_i2c_byte_generic I2C byte read error - Retrying. I2C byte read error. e1000_write_i2c_byte_generic I2C byte write error. e1000_i2c_bus_clear e1000_init_mac_params_82575 e1000_sgmii_uses_mdio_82575 PHY module has not been recognized e1000_reset_hw_82580 PCI-E Master disable polling has failed. Masking off all interrupts Auto Read Done did not complete Could not reset MDICNFG based on EEPROM e1000_reset_mdicnfg_82580 NVM Read Error e1000_reset_hw_82575 PCI-E Set completion timeout has failed. Issuing a global reset to MAC e1000_reset_init_script_82575 Running reset init script for 82575 e1000_setup_copper_link_82575 Error resetting the PHY. e1000_setup_serdes_link_82575 Configuring Autoneg:PCS_LCTL=0x%08X Configuring Forced Link:PCS_LCTL=0x%08X e1000_shutdown_serdes_link_82575 e1000_power_up_serdes_link_82575 e1000_check_for_link_82575 Error configuring flow control e1000_get_pcs_speed_and_duplex_82575 2500 Mbs, Full Duplex e1000_read_mac_addr_82575 e1000_config_collision_dist_82575 e1000_clear_vfta_350 e1000_get_link_up_info_82575 e1000_acquire_swfw_sync_82575 Driver can't access resource, SW_FW_SYNC timeout. e1000_release_swfw_sync_82575 e1000_init_phy_params_82575 e1000_acquire_phy_82575 e1000_get_cfg_done_82575 MNG configuration cycle has not completed. e1000_release_phy_82575 e1000_phy_hw_reset_sgmii_82575 Soft resetting SGMII attached PHY... e1000_read_phy_reg_sgmii_82575 PHY Address %u is out of range e1000_write_phy_reg_sgmii_82575 PHY Address %d is out of range e1000_read_phy_reg_82580 e1000_write_phy_reg_82580 e1000_get_phy_id_82575 Vendor ID 0x%08X read at address %u PHY address %u was unreadable e1000_check_for_link_media_swap e1000_set_d0_lplu_state_82575 e1000_set_d0_lplu_state_82580 e1000_set_d3_lplu_state_82580 e1000_acquire_nvm_82575 Nvm bit banging access error detected and cleared. e1000_release_nvm_82575 e1000_valid_led_default_82575 e1000_clear_hw_cntrs_82575 e1000_validate_nvm_checksum_82580 e1000_validate_nvm_checksum_with_offset NVM Checksum Invalid e1000_update_nvm_checksum_82580 NVM Read Error while updating checksum compatibility bit. NVM Write Error while updating checksum compatibility bit. e1000_update_nvm_checksum_with_offset NVM Read Error while updating checksum. NVM Write Error while updating checksum. e1000_validate_nvm_checksum_i350 e1000_update_nvm_checksum_i350 __e1000_access_emi_reg e1000_i2c_start e1000_i2c_stop e1000_clock_in_i2c_byte e1000_clock_in_i2c_bit e1000_get_i2c_data e1000_clock_out_i2c_byte e1000_get_i2c_ack I2C ack was not received. e1000_clock_out_i2c_bit I2C data was not set to %X e1000_set_i2c_data Error - I2C data was not set to %X. e1000_raise_i2c_clk e1000_lower_i2c_clk e1000_init_function_pointers_vf e1000_init_mac_params_vf e1000_setup_link_vf e1000_get_bus_info_pcie_vf e1000_reset_hw_vf Issuing a function level reset to MAC e1000_init_hw_vf e1000_check_for_link_vf e1000_get_link_up_info_vf 1000 Mbs, 100 Mbs, 10 Mbs, Full Duplex Half Duplex e1000_update_mc_addr_list_vf MC Addr Count = %d Hash value = 0x%03X e1000_hash_mc_addr_generic e1000_init_nvm_params_vf e1000_init_phy_params_vf e1000_read_mbx e1000_write_mbx e1000_check_for_msg e1000_check_for_ack e1000_check_for_rst e1000_read_posted_mbx e1000_write_posted_mbx e1000_poll_for_msg e1000_poll_for_ack e1000_null_mbx_rw_msg e1000_null_mbx_check_flag e1000_read_mbx_vf e1000_obtain_mbx_lock_vf e1000_write_mbx_vf e1000_check_for_msg_vf e1000_check_for_ack_vf e1000_check_for_rst_vf e1000_read_mbx_pf e1000_obtain_mbx_lock_pf e1000_write_mbx_pf e1000_check_for_msg_pf e1000_check_for_ack_pf e1000_check_for_rst_pf e1000_acquire_swfw_sync_i210 Driver can't access resource, SW_FW_SYNC timeout. e1000_release_swfw_sync_i210 e1000_read_nvm_srrd_i210 e1000_write_nvm_srwr_i210 e1000_validate_nvm_checksum_i210 e1000_update_nvm_checksum_i210 EEPROM read failed NVM Read Error while updating checksum. NVM Write Error while updating checksum. e1000_get_flash_presence_i210 e1000_update_flash_i210 Flash update time out Flash update complete e1000_read_xmdio_reg e1000_init_hw_i210 e1000_get_hw_semaphore_i210 Driver can't access device - SMBI bit is set. Driver can't access the NVM e1000_write_nvm_srwr nvm parameter(s) out of bounds e1000_pool_flash_update_done_i210 e1000_init_nvm_params_i210 e1000_acquire_nvm_i210 e1000_release_nvm_i210 e1000_valid_led_default_i210 NVM Read Error e1000_read_invm_i210 MAC Addr not found in iNVM NVM word 0x%02x is not mapped. e1000_read_invm_word_i210 Read INVM Word 0x%02x = %xRequested word 0x%02x not found in OTP __e1000_access_xmdio_reg e1000_get_cfg_done_i210 MNG configuration cycle has not completed.  2.5.3-k          OH*d@FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0)FreeBSD clang version 6.0.0 (tags/RELEASE_600/final 326565) (based on LLVM 6.0.0).symtab.strtab.shstrtab.rela.text.rela.rodata.relaset_modmetadata_set.relaset_sysinit_set.relaset_sysctl_set.rodata.str1.1.rodata.cst16.rela.data.bss.comment.note.GNU-stack $2 9 T Y     $IX _ z  t   0% /":Gk t{ < U n73 |# ( - D4G Z3iu    :3    E   : ?Sa h       5 :gu |    %3 : U Z* 8 GU \ w |   6*R e   x 4  ] O O, O1 ] g   1 1 1  4  ># >> >C g n w ~  y    8 N   2( ; 3J V j o t :z   3  ; O  :   s 1 L [  8  8 $ 8.     79,z 8   8* 79[ 8e~,,&yT 8^  >  T 8YNg 8lKz 8N 8N 8M 8,38D  X ] b 0Fiv3  )  `GA   * 6 D[c"z I$ `u: PE k `v    p%  m% K   - 8)+n6 AIy  j  pk33 D I N Ul }       /    O  [    y (  - 2 9P  a  f k r                  4  E 1 J O Vm I ~ V    x            :  7  <  A :H             pK . _ 7 d  i o P  Y     r      M   $  )  . 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