A pfSense roadmap
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Ehhhhhhh. Sounds like so much work…. haha
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The PCengines APU is 64 bit, 2GB or 4GB real memory, 3 NICs and in that price range.
But the Realtek NICs are awful.
Be aware that Pascal is on record about engineering a replacement in the short-term. (EOY, I imagine.) The next PC Engines board has a Jaguar (so: AES-NI) 2 or 4 core CPU, 2 or 4GB RAM (ECC on the 4GB model) and (wait for it), Intel NICs (I imagine these will be i217/218 class.)
I took this into consideration for 3.0.
Our low-end strategy is the C2000 Avoton/Rangeley series of SoCs.
Roadmap looks good. Separating the GUI presentation code from the input validation from the backend implementation is really needed. Then other bits like pfCenter can have well-defined interfaces to use to make multi-system config changes and get monitoring data…
If Python turns out to be the major selected language for a lot of the code, then thanks for the opportunity to learn another language ;)
What ever happened to good old that some of us know (and loved?) Cobol, Fortran :-\I wrote a lot of Fortran in my youth.
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Thanks for sharing with us the road map. It's nice to know where the chauffeur is taking us.
Any mile stone timeline goals, estimates, hopes, wishful thinking, anything?
Thanks
New hardware in q3. That's all the hint I'll give.
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I might consider it - I have time now. I used to be pretty good at it, relatively speaking (-;
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It would be great to see Apinger's issues called out with a action plan sooner vs later as I have provider issues and graphs that are unusable in helping to get these issues fixed
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It would be great to see Apinger's issues called out with a action plan sooner vs later as I have provider issues and graphs that are unusable in helping to get these issues fixed
There's always cacti, etc. pfSense doesn't have to do everything. (Not that I don't want apinger fixed/replaced, but if it's broken get another tool.)
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It would be great to see Apinger's issues called out with a action plan sooner vs later as I have provider issues and graphs that are unusable in helping to get these issues fixed
apinger needs a re-write. It's garbage code.
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Wow!
There is just something magical reading the project map for 3.0 while feasting on a Cadbury's almonds and raisin chocolate bar.
But…any consideration for the Wireless ISP guys? No MPLS implementation? No MIPS hardware as yet? Can these be options for consideration for small ISP types?
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Fortran IV - holes in punched cards can be seen. And the 6 position is marked usual. ;)
Python? Programming with spaces? Loss/extra space and the program behaves unpredictably? Forget copy/paste, move pieces of code, and so on?
Great… :( -
Wow!
There is just something magical reading the project map for 3.0 while feasting on a Cadbury's almonds and raisin chocolate bar.
But…any consideration for the Wireless ISP guys? No MPLS implementation? No MIPS hardware as yet? Can these be options for consideration for small ISP types?
Did I say there would not be MPLS, or GRE support?
No, I did not. It's a path, jtls.
In any case, 2.x is always an option on existing hardware.
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Fortran IV - holes in punched cards can be seen. And the 6 position is marked usual. ;)
Python? Programming with spaces? Loss/extra space and the program behaves unpredictably? Forget copy/paste, move pieces of code, and so on?
Great… :(If it forces us to maintain proper style and spacing, it's not a bad thing.
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Fortran IV - holes in punched cards can be seen. And the 6 position is marked usual. ;)
Python? Programming with spaces? Loss/extra space and the program behaves unpredictably? Forget copy/paste, move pieces of code, and so on?
Great… :(If it forces us to maintain proper style and spacing, it's not a bad thing.
python is a lot like lisp without the parenthesis. Once you figure that out, it gets easy.
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@gonzopancho:
The next PC Engines board has a Jaguar (so: AES-NI) 2 or 4 core CPU, 2 or 4GB RAM (ECC on the 4GB model) and (wait for it), Intel NICs (I imagine these will be i217/218 class.)
Intel NIC's? That is awesome, where did you see this?
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[…]and the program behaves unpredictably?[…]
Forgot something:
Unpredictable behavior will most likely be caught by the copious amount of unit tests we'll surely be adding during the rewrite.
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@gonzopancho:
The next PC Engines board has a Jaguar (so: AES-NI) 2 or 4 core CPU, 2 or 4GB RAM (ECC on the 4GB model) and (wait for it), Intel NICs (I imagine these will be i217/218 class.)
Intel NIC's? That is awesome, where did you see this?
Pascal told Chrs months ago.
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Sounds like nice hardware. These will work well when its 32C outside, hotter inside and no airconditioning? (Its a serious question)
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I don't design the PC Engines boards.
The RCC-VE & RCC-DF will.
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Totally
@gonzopancho:
apinger needs a re-write. It's garbage code.
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rewrite can't happen soon enough dual wan failover is what brought me to Pfsense on my connections it no longer works
