Watchguard XTM 5 Series

[frillyfeather]

Hi, I am trying to find some information about ACPI and AML to be able to generate this for the CPU I've put in (Xeon L5420) but since there's over 1000 post here I'm not finding this easy! How would one go about finding the data that goes in to this file so it can be correctly generated?

Right I see you basically have to boot and test out various values to see if they work and the system is stable, sounds like a fun weekend project...

[frillyfeather]

So I created the file, built it into the BIOS, flashed it, linux seems to think it works (cpupower) but pfsense shows:

est0: failed to enable SpeedStep
est1: failed to enable SpeedStep
est2: failed to enable SpeedStep
est3: failed to enable SpeedStep

I've also tried copying the .aml to the device and loading it in /boot/loader.conf.local and get the same error, any way to debug this further?

[stephenw10]

Yup, pretty much! Some CPUs seem very difficult to find any 'official' values for. Best guesses seem to work. Mostly.

The ones I did I started with something that was close and added or modified the P state definitions. IIRC there were some ACPI errors/warnings the compiler threw put I was able to correct too.

[stephenw10]

Is Speedstep enabled in the BIOS? It's disabled by default IIRC

[frillyfeather]

@stephenw10 I get 5 warnings, 48 remarks, the only ones relating to processor are to use device() instead - which I haven't done, assuming that the legacy processor() one is still OK. I do not have a speedstep option in BIOS, I did look around for one but didn't see anything, this is what I have in the CPU menu:
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[stephenw10]

Hmm, you can use cpuctl to read the CPU register directly once it's booted. Been a while since I've tried that.

Normally if Speedstep is disabled though est shows it's unable to attach. Hmm.

[frillyfeather]

@stephenw10 cpuctl doesn't seem to be a default installed package

I have tried loading the default unlocked BIOS and comparing it with my modified BIOS in linux, with the default one cpupower gets nothing, with my modified one it gets the values I put in and seemingly it can change the frequency, it just appears to be pfsense that can't for some reason

[stephenw10]

cpuctl is a kernel module, the actual command is cpucontrol

[2.7.0-RELEASE][admin@t70.stevew.lan]/root: kldstat
Id Refs Address                Size Name
 1   45 0xffffffff80200000  339d810 kernel
 2    1 0xffffffff8359e000   5ba0d8 zfs.ko
 3    1 0xffffffff83b5a000     76f8 cryptodev.ko
 4    1 0xffffffff84120000     2220 cpuctl.ko
 5    1 0xffffffff84123000     3248 ichsmb.ko
 6    1 0xffffffff84127000     2178 smbus.ko
 7    1 0xffffffff8412a000     5ee0 ig4.ko
 8    1 0xffffffff84130000     9288 aesni.ko
 9    1 0xffffffff8413a000     20e8 coretemp.ko
10    1 0xffffffff8413d000    13808 dummynet.ko
[2.7.0-RELEASE][admin@t70.stevew.lan]/root: cpucontrol
Usage: cpucontrol [-vh] [-d datadir] [-m msr[=value] | -i level | -i level,level_type | -e | -u] device

[stephenw10]

I don't recall exactly which bit it is but you can read the MSR contaning it to check as shown here: https://forum.netgate.com/post/338671

[frillyfeather]

@stephenw10 Doing that I get:

MSR 0x198: 0x47174717 0x06004717

Which is the top speed I have in my DSDT:

				Name (_PSS, Package (0x04)	// Performance Supported States
				{							// Values below for Intel Xeon L5420
					Package (0x06)
					{
						2500, 			// f in MHz
						50000, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00004717, 	// value written to PERF_CTL; fid=71 (0x47), vid=23 (0x17)
						0x00004717 		// value of PERF_STATE after successful transition; fid=71 (0x47), vid=23 (0x17)
					},

					Package (0x06)
					{
						2333, 			// f in MHz
						45800, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00000715, 	// value written to PERF_CTL; fid=0x07, vid=0x15
						0x00000715 		// value of PERF_STATE after successful transition; fid=0x07, vid=0x15
					},
...

Not sure which register the lock bit would be in (or where a list of registers are)

When I was trying c2ctl on linux, I was getting this:

      Current  Target    Min.    Max.
FID:       71      10      71      71
VID:       23      30      23      23
ESIT_ENABLE = FALSE    ESIT_LOCK = TRUE

Which was prior to having inserted the dsdt, does this mean that speedstep is locked and can't be used?

[stephenw10]

Yes, it's disabled and locked. I unlocked it and enabled it in the BIOS mod I did initially: https://forum.netgate.com/post/338671
Looking through my notes from 10 years ago now but... limited!

You could just start with the unlocked bios.

[frillyfeather]

@stephenw10 I started with the "unlocked 1.9 BIOS" which I got from this thread, I assume your BIOS had the filename "xtm5_83.rom"? If so, looked through that with amibcp and I do not see a "speedstep" option in the BIOS?

[stephenw10]

Ok pretty sure it's bits 16 (enable) and 20 (lock) from MSR 0x1A0:

[2.7.0-RELEASE][admin@t70.stevew.lan]/root: cpucontrol -m 1a0 /dev/cpuctl0
MSR 0x1a0: 0x00000000 0x00850081

EIST is enabled in that box:

[2.7.0-RELEASE][admin@t70.stevew.lan]/root: dmesg | grep est
est0: <Enhanced SpeedStep Frequency Control> on cpu0
[2.7.0-RELEASE][admin@t70.stevew.lan]/root: sysctl dev.cpu.0.freq_levels
dev.cpu.0.freq_levels: 1601/2000 1600/2000 1520/1900 1440/1800 1360/1700 1280/1600 1200/1500 1120/1400 1040/1300 960/1200 880/1100 800/1000 720/900 640/800 560/700 480/600

[frillyfeather]

@stephenw10 Well this is an interesting turn of events, the "unlocked 1.8 unlocked 1.9" BIOS posted by @t-rexky is actually anything but unlocked, I injected my DSDT into your seemingly 10 year older BIOS and instantly from pfSense, speedstep is now working. The UI is a bit jumpy, adding/removing the CPU speed output but it does seem to be working, many thanks!

For anyone else that wants it, I attach my attempts at a xeon L5420 DSDT power table.

ACPI_AML_L5420_B3.zip

[stephenw10]

Nice! Yeah IIRC t-rexky enabled everything that could be enabled in the BIOS setup but I don't think Speedstep/EIST was ever an option there. I had to set the bits in the BIOS directly.

[tiggymiggy]

@frillyfeather can you please post your modified ROM for the L5420? I want to get this CPU too.

[stephenw10]

They are using the BIOS mod I did ages ago, which has speedstep enabled, in combination with that attached dsdt file.

[dlucas46]

@tiggymiggy

Be warned if you use the Xeon you will get weird temperature readings because the coretemp module of the kernel gets the CPU wrong and sets the wrong thermal values.
I have not yet managed to compile a 2.7 kernel module to fix it.

It it's purely cosmetic but I find it annoying.

[tiggymiggy]

@stephenw10 In other words the same solution that you shared with the e8400?

[stephenw10]

Yes. Just using a different dsdt file.