Watchguard XTM 5 Series

stephenw10

Ah nice result. :)
For many people a low to intermediate load is where a Core2duo is likely to operate most of the time. I had thought it might be of some benefit there.

Did you add P-states specific for your CPU? I recall I had some difficulty finding the 'official' values but there were plenty of suggestions on both overclocking and underclocking forum threads.

Steve

t-rexky

Thank you :D

This was all done by setting the registers manually. I made an attempt at a custom DSDT yesterday and it was a total failure. I then realized that even if I decompile and recompile the factory DSDT with no changes it does not work. It completely messes up the box, as in network ports are not recognized by the kernel, etc. I have to figure out why this does not work first…

stephenw10

Ah, interesting I never tried that.

I definitely did have it working at one time. Failed to keep better notes. :-[

Steve

DeLorean

@iJay-XTM5:

Unfortunately, the unit is a bit too noisy for my home despite using WGXepc64 for slowing down the fans. The noise appears to be originating from the CPU fan(s), which I understand are controlled by the bios. Unlike the bios in other systems, this unit 's bios is dated 4/26/2010.
I'd appreciate suggestions on how to get the bios unlocked/CPU fans silenced.

If you use Y splittercables, then you can combine all the fan connectors to 1 connector,
and connect this connector to the chassis fan connector on the mainboard, then you can use WGXepc64 to lower the fanspeed as low as you want.
Keep in mind, that lowering the fanspeed too much, the cpu temp will raise under load.

Grtz
DeLorean

Billyboy

Hi Peter, can please you give me some more details aubout the VGA cable?
I need to have the same!

Regards

Christian

@t-rexky:

The on-board VGA header definitely works, and it works very well. I made a custom cable with a connector I got from digiKey and it's been extremely useful in playing with the box. The front USB ports work well with USB keyboards and mice as well, so the box becomes a fully functional PC with on-board video.

Cheers,
Peter.

iJay-XTM5

@DeLorean:

If you use Y splittercables, then you can combine all the fan connectors to 1 connector,
and connect this connector to the chassis fan connector on the mainboard, then you can use WGXepc64 to lower the fanspeed as low as you want.
Keep in mind, that lowering the fanspeed too much, the cpu temp will raise under load.

Grtz
DeLorean

I was initially hoping to have independent control of the fans based on temperature, but perhaps I can get to a balanced medium.
Thanks for the response, I'll get splitter cables ordered.

iJay

wildio

Hi everyone! Thanks for all the info in here. With it, I've managed to convert an XTM 515 to a very nice Sophos box. However, I keep getting stuck on upgrading the memory. I've tried everything I see here and nothing is working. Does anyone have a link or part number for the memory I will need? Would be super awesome! Don't think Amazon is going to let me return anything else for another 10 years probably.

stephenw10

"Just worked" with whatever I've put in it though I've never tried to get it to run 8GB. Not sure I've ever tried 4GB either, I just used what was at hand.

Currently running 2x Nanya NT1GT64U8HB0BY-25D, 1GB 2RX8 PC-2-6400U-666.

Steve

wildio

@stephenw10:

"Just worked" with whatever I've put in it though I've never tried to get it to run 8GB. Not sure I've ever tried 4GB either, I just used what was at hand.

Currently running 2x Nanya NT1GT64U8HB0BY-25D, 1GB 2RX8 PC-2-6400U-666.

Steve

Thanks, Steve! That helps a lot. That's different than what I've been trying to use.

t-rexky

@Billyboy:

Hi Peter, can please you give me some more details aubout the VGA cable?
I need to have the same!

Regards

Christian

Hi Christian,

Sure. I originally wanted to make an adapter cable but then decided that it was not worth it since I'd be only using it temporarily. So I ended up cutting one end off a standard DB15 VGA cable and soldering the pins to a connector that was not meant to be soldered to. If you do the same, make sure that you remove the pins from the connector before soldering to avoid the plastic meting. The connector I ordered was DigiKey P/N 609-2736-ND. It is the right type to fit the board header. When you make the cable, the pinout to use is as follows:

| **DB15 pin ** | Header Pin |
| 1 | 1 |
| 2 | 3 |
| 3 | 5 |
| 4 | N/C |
| 5 | N/C |
| 6 | 2 |
| 7 | 4 |
| 8 | 6 |
| 9 | N/C |
| 10 | 10 |
| 11 | N/C |
| 12 | 11 |
| 13 | 7 |
| 14 | 9 |
| 15 | 12 |

Hope that helps,
Peter.

mahave

have just grabbed a watchguard xtm 515
Has thrown a 60gb hdd into it to pfsense.

has tried to put "pfSense-CE-memstick-serial-2.4.3-RELEASE-amd64.img" onto the CF card. When it's loaded, it's get stuck on line: Trying two mount root from ufs: / dev / ufs / FreeBSD_Install [ro, noatime] …

Full log: https://pastebin.com/Q5eitjBZ
Sometimes I do not get any console output and just a black screen after bios screen. Where it does something behind it can i see on the cursor.

The bios is the stock "WG BIOS 1.3"

Have tried to format the disk, second disk, look in bios for settings (view only mode ..)
Have tried to load "pfSense-CE-2.3.5-RELEASE-4g-amd64-nanobsd.img" into hdd - but without success and stuck in last line - Log: https://pastebin.com/ahY7NgsP

What can i do to put pfsense 2.4.3 on the watchguard?

stephenw10

That's the point where it switches to the primary only console. Are you sure you used the serial memstick image? If you have used the standard VGA image that's exactly what you would see.

Steve

mahave

@stephenw10:

That's the point where it switches to the primary only console. Are you sure you used the serial memstick image? If you have used the standard VGA image that's exactly what you would see.

Steve

It is the memstick serial version i have used :/

t-rexky

@stephenw10:

Ah, interesting I never tried that.

I definitely did have it working at one time. Failed to keep better notes. :-[

Steve
[/quote]

Well, this was a pretty steep learning curve but I can confirm that I now have a modified DSDT that fully supports SpeedStep on the stock CPU. And yes, I can confirm that SpeedStep does indeed work as intended.

I also fiddled quite a bit with C states, but the chipset really only supports C1 in a desktop configuration, so there is absolutely nothing to be gained in terms of idle power consumption: 46W at idle is it! Earlier today I had a Eureka moment thinking I can get lower idle power by enabling CPUSLP#, but as it turns out it is already enabled. Besides, I think the CPU actually drops into C1E state when idle so the power consumption gets as low as it possibly can already. But, of course, I could be talking out of my orifice since I really don't quite know enough about this.

My original issue with DSDT failing was Linux related: I was using a DSDT override method that is apparently no longer supported. Switching to Grub based override of DSDT fixed that issue. Next step for me will be to create and flash a custom BIOS image with the modified DSDT. I intend to create two versions: one for the stock CPU and one for my Q9505S CPU.

corvey

@t-rexky:

Well, this was a pretty steep learning curve but I can confirm that I now have a modified DSDT that fully supports SpeedStep on the stock CPU. And yes, I can confirm that SpeedStep does indeed work as intended.

I also fiddled quite a bit with C states, but the chipset really only supports C1 in a desktop configuration, so there is absolutely nothing to be gained in terms of idle power consumption: 46W at idle is it! Earlier today I had a Eureka moment thinking I can get lower idle power by enabling CPUSLP#, but as it turns out it is already enabled. Besides, I think the CPU actually drops into C1E state when idle so the power consumption gets as low as it possibly can already. But, of course, I could be talking out of my orifice since I really don't quite know enough about this.

My original issue with DSDT failing was Linux related: I was using a DSDT override method that is apparently no longer supported. Switching to Grub based override of DSDT fixed that issue. Next step for me will be to create and flash a custom BIOS image with the modified DSDT. I intend to create two versions: one for the stock CPU and one for my Q9505S CPU.

From what I remember using my old firebox, the stock power supply was very inefficient. It wasn't until I switched to a picoPSU and an efficient Toshiba laptop power brick that I saw the wattage drop from 45-50 watts to 25watts.

stephenw10

Yeah, it's probably not great at those Wattage levels despite being a smaller than stock PSU for the original Lanner device.

Steve

t-rexky

I now have a tested and working version of BIOS for the most recent XTM 5 Series hardware that shipped with E3400 CPU, that includes a number of tweaks and also implements SpeedStep for the E3400 CPU. If anyone is interested I can post a link to the BIOS image. Here is my full list of changes:

XTM515-BIOS1.3-UNLOCKED1.8:
Changed 'Sign On Message' to include 'Unlocked v1.8 PT / E3400'.
Corrected ACPI version help string line breaks in "Enabled RSDP pointers to 64-bit [...]".

XTM515-BIOS1.3-UNLOCKED1.7:
Changed 'Sign On Message' to include 'Unlocked v1.7 PT / E3400'.
Modified LCD boot string from "WG BIOS 1.3" to "Firewall UTM" in module 1B (Single Link Arch BIOS).

XTM515-BIOS1.3-UNLOCKED1.6:
Changed 'Sign On Message' to include 'Unlocked v1.6 E3400 PT'.
Created two ROM branches, one for E3400 CPU and one for Q9505S CPU.

XTM515-BIOS1.3-UNLOCKED1.5:
Changed 'Sign On Message' to include 'Unlocked v1.5 PT'.
Enabled 'PCIPnP' and 'Chipset' menus.
Enabled 'CPU Configuration' submenu in 'Advanced' menu.
Enabled 'ACPI Configuration' submenu in 'Advanced' menu.

XTM515-BIOS1.3-UNLOCKED1.4:
Updated platform 11 CPUID 1067a microcode to version a0b.

XTM515-BIOS1.3-UNLOCKED1.3:
Disabled 'Lan ByPass Control' submenu in 'Advanced' menu.
Modified BIOS Strings from 'Port0 AHCI Speed limit to' to 'Port0 AHCI Speed limit' for Port0 to Port3.

XTM515-BIOS1.3-UNLOCKED1.2:
Changed 'Aways CF Card Boot' to 'Show' in 'Advanced' menu.

XTM515-BIOS1.3-UNLOCKED1.1:
Unlocked the BIOS by changing 'User Access Level' to 03 in 'Security' menu.

A Former User

This post is deleted!

stephenw10

Interesting so does this provide voltage/frequency steps for only the supported CPU? Or does it just try to apply those to whatever is installed?

I don't recall having to set a particular CPU type when I was messing about with this.

Steve

t-rexky

I am struggling to keep awake, so this will be a quick post in response to stephenw10 and 747Builder.

I spent q bit of time dissecting various BIOS flavours, including the XTM515. I reached a conclusion that it would be very difficult, if not impossible to implement a truly "universal" BIOS. This is primarily because most BIOS builds seem to include a baseline universal CPU ACPI information in the DSDT table, and then dynamically create the appropriate SSDT tables at boot. Those SSDT tables are created with code that resides in the "SLAB" module of the AMI BIOS - the Single Link Arch BIOS. The XTM515 BIOS is missing the required code so the easiest option is to create a separate BIOS image for each CPU model. This is effectively what I have done: the E3400 BIOS image has the required E3400 P-states programmed into the DSDT table, including the FID, VID, frequency and (estimated) power consumption. Similarly the Q9505S BIOS image has the required Q9505S P-states programmed into the DSDT table.

For each CPU model a new DSDT table has to be created and compiled, then merged into the baseline BIOS to replace the old DSDT table and to create a CPU specific BIOS image. I know that the Q9505S BIOS should work fine with Q9505, Q9505S, Q9550 and Q9550S CPUs, except the power will be way off for the non-S models. But the FID, VID and frequencies will be correct.

As an example, I am enclosing below a single CPU core DSDT excerpt for each of the above two CPUs. Please ignore the FID and VID numbers quoted in the comments as I have not fixed them yet to align with the actual FID and VID values in the code. This is left-over copy & paste-a-tis and my chronic lack of time!

CPU1 for E3400 with 4 P-states:

        Processor (CPU1, 0x01, 0x00000810, 0x06)
		{
				Name (_PPC, 0x00)

				Name (_PCT, Package (0x02)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 	// PERF_CTL
							0x10,              	// Bit Width
							0x00,               // Bit Offset
							0x00000199, 		// Address
							,)
					},

					ResourceTemplate ()
					{
						Register (FFixedHW, 	// PERF_STATUS
							0x10,	            // Bit Width
							0x00,    			// Bit Offset
							0x00000198, 		// Address
							,)
					}
				})

			   	Name (_CST, Package (0x02)
				{
					0x01,
					Package (0x04)
					{
						ResourceTemplate ()
						{
							Register (FFixedHW,
								0x01,               // Bit Width
								0x02,               // Bit Offset
								0x0000000000000000, // Address
								0x01,               // Access Size
								)
						},

						1,			// C State Type
						2,			// Transition latency in us
						25000		// Power Consumption in mW
					}
				})

				Name (_PSS, Package (0x04)	// Values below for Intel Celeron E3400
				{
					Package (0x06)
					{
						2600, 			// f in MHz
						65000, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00000D24, 	// value written to PERF_CTL; fid=13, vid=36
						0x00000D24 		// value of PERF_STATE after successful transition; fid=13, vid=36
					},

					Package (0x06)
					{
						2000, 			// f in MHz
						53800, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00000A1E, 	// value written to PERF_CTL; fid=13, vid=36
						0x00000A1E 		// value of PERF_STATE after successful transition; fid=13, vid=36
					},

					Package (0x06)
					{
						1600, 			// f in MHz
						47500, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x0000081A, 	// value written to PERF_CTL; fid=13, vid=36
						0x0000081A 		// value of PERF_STATE after successful transition; fid=13, vid=36
					},

					Package (0x06)
					{
						1200, 			// f in MHz
						42000, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00000616, 	// value written to PERF_CTL; fid=13, vid=36
						0x00000616 		// value of PERF_STATE after successful transition; fid=13, vid=36
					}
				})
		}

CPU1 for Q9505S with 6 P-states:

        Processor (CPU1, 0x01, 0x00000810, 0x06)
		{
				Name (_PPC, 0x00)

				Name (_PCT, Package (0x02)
				{
					ResourceTemplate ()
					{
						Register (FFixedHW, 	// PERF_CTL
							0x10,              	// Bit Width
							0x00,               // Bit Offset
							0x00000199, 		// Address
							,)
					},

					ResourceTemplate ()
					{
						Register (FFixedHW, 	// PERF_STATUS
							0x10,	            // Bit Width
							0x00,    			// Bit Offset
							0x00000198, 		// Address
							,)
					}
				})

			   	Name (_CST, Package (0x02)
				{
					0x01,
					Package (0x04)
					{
						ResourceTemplate ()
						{
							Register (FFixedHW,
								0x01,               // Bit Width
								0x02,               // Bit Offset
								0x0000000000000000, // Address
								0x01,               // Access Size
								)
						},

						1,			// C State Type
						2,			// Transition latency in us
						12000		// Power Consumption in mW
					}
				})

				Name (_PSS, Package (0x06)	// Values below for Intel Core 2 Quad Q9595S
				{
					Package (0x06)
					{
						2833, 			// f in MHz
						65000, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x0000481E, 	// value written to PERF_CTL; fid=48, vid=1E
						0x0000481E 		// value of PERF_STATE after successful transition; fid=48, vid=1E
					},

					Package (0x06)
					{
						2666, 			// f in MHz
						60100, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x0000081C, 	// value written to PERF_CTL; fid=9, vid=28
						0x0000081C 		// value of PERF_STATE after successful transition; fid=9, vid=28
					},

					Package (0x06)
					{
						2500, 			// f in MHz
						56400, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x0000471B, 	// value written to PERF_CTL; fid=6, vid=22
						0x0000471B 		// value of PERF_STATE after successful transition; fid=6, vid=22
					},

					Package (0x06)
					{
						2333, 			// f in MHz
						52000, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00000719, 	// value written to PERF_CTL; fid=9, vid=28
						0x00000719 		// value of PERF_STATE after successful transition; fid=9, vid=28
					},

					Package (0x06)
					{
						2166, 			// f in MHz
						48600, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00004618, 	// value written to PERF_CTL; fid=9, vid=28
						0x00004618 		// value of PERF_STATE after successful transition; fid=9, vid=28
					},

					Package (0x06)
					{
						2000, 			// f in MHz
						44700, 			// P in mW
						10, 			// Transition latency in us
						10, 			// Bus Master latency in us
						0x00000616, 	// value written to PERF_CTL; fid=9, vid=28
						0x00000616 		// value of PERF_STATE after successful transition; fid=9, vid=28
					}
				})
		}

So in summary, the two BIOS images I created should be only installed on XTM units equipped with the specific CPUs!

Peter.