@bingo600
Got a bit interested here ...
According to the Intel i350 reference design here (last entry / bottom):
Document: 323852
https://www.intel.com/content/www/us/en/products/details/ethernet/gigabit-controllers/i350-controllers/docs.html?s=Newest&p=2
Page 4 - SMBus interface
U7 (The i350 controller chip) , is connected directly to J42 (PCIE slot) , with just a couple of 10K pullup's.
So B5 & B6 aren't connected directly to a config eeprom , but to the i350.
On Page 7 - Support circuits.
We see that U7 (i350) has connection to a SPI Flash , and an SPI EEPROM.
I'd assume the SPI Flash holds Boot Code & Other stuff.
And according to - The i350 Datasheet - Page 12
Document : 333171
https://www.intel.com/content/www/us/en/products/details/ethernet/gigabit-controllers/i350-controllers/docs.html?s=Newest&p=2
The EEPROM holds the size of the SPI FLASH flashzise , and prob. other goodies.
So i assume that : What is read via the PCie SMBus , and confuses the bootcycle is residing in either the SPI EEPROM or the SPI FLASH that is connected to the i350.
And since it is the i350 that is responsible for SMBus communication, there's probably no "Easy fix" like lifting an I2C eeprom leg or two , in order to avoid unmasking PB5 & PB6.
Fun stuff ....
Hmm ... In the DS pg. 99 an OEM VPD area is described
1684f166-8b81-4b31-87b3-cefc42c961ac-image.png
Maybe setting the word at 0x2F to 0xFFFF , would skip the Dell OEM information , and stop confusing the PC ??
/Bingo